When I was contacted last year about making an OpenRISC-based SoC for an SDR platform I didn’t have to think twice. I have been curious about SDR and being able to combine that with my knowledge of Open Source FPGA work seemed like a great opportunity. After having talked to Ebrahim Bushehri, CEO of Lime Microsystems, I was even more eager as it turned out that this was a company that understood open source and used it as a vital part of their business strategy. By releasing all the support infrastructure such as development boards, drivers, specifications and software as open source, as well as actively collaborating with high-profile open source projects such as Parallella, Novena and OpenRISC, they are able to focus on their core business of providing world class highly configurable RF ASICs.

In June 2014 I went to visit Lime Microsystems in Guildford, where I got to meet the team and was shown early schematics of what would become the STREAM board. The vision that Ebrahim had for the the board was to enable the myriad of software engineers to be able to do interesting RF-enabled applications with the LMS ASICs, without having to deal so much with the intricate details of the hardware. In a way, this is just what the LMS ASICs themselves do for me as an FPGA designer, as I can enjoy a simple digital interface without having to dive into the vastly more intricate details of analog hardware. Working for Qamcom, a company specialized in the field of high performance RF systems, I had also a vast supply of instruments and experienced colleagues to help me with the testing and theories of radio communication, which was very helpful whenever I found myself lost in sampling theorems and modulation techniques.

After throwing some ideas back and forth it seemed like we shared a common idea of what the board should be able to do. I went back home to Sweden, we agreed on a time plan and I got to work with implementing the FPGA logic on a prototype board, while the engineers at Lime were finishing up the last details of the final STREAM boards. By February 2015 we had something running on the STREAM boards that was close to the original vision. The FPGA was now able to boot Linux, transmit samples between the onboard memories and the RF ASIC, and could be controlled from either a computer connected through USB or software running directly on the OpenRISC CPU in the FPGA. A few of the peripherals were unfortunately not connected due to lack of time.

So let’s dive into the architecture.


The SoC running on the FPGA is a fairly standard setup for an OpenRISC-based system. It has a UART for standard input/output, an Ethernet MAC, memory controllers and a debug interface available through JTAG. The parts specifically tailored for the LMS ASIC is an SPI interface for accessing the LMS registers and tx/rx interfaces for transmitting I/Q data to and from the LMS. The tx/rx interfaces are connected to one of the DDR2 memories through DMA controllers. By using one of the DDR2 memories exclusively for transmitting I/Q samples, we can ensure that no samples are lost even when the main operating system is under heavy load. The received I/Q data stream can also be transmitted through the FX3 USB controller to a PC. There is also a DVI controller for presenting a frame buffer through the HDMI connector. This feature is currently under testing and is not yet available in the provided sources.

By using as many existing and well-proven components as possible, the maintenance burden is shifted out from the project and improvements to each components can be pulled in as they seem fit. The only parts in the FPGA specific to the STREAM board are a thin I/O layer towards the digital I/Q interfaces. A streaming DMA component was also developed as part of the project, and that one has already seen use in other places during which a Linux driver was also developed. This is a great indication of the benefits of open source.


When we want to transmit data over the air, we do that by providing the LMS ASIC with a stream of I/Q samples. By default tx data is provided by a test pattern generator that sends four pairs of I/Q data that implements a continuous 30.72/4/2MHz sine wave in the frequency plane. This is mainly intended to provide the user with a known signal to see that the transmit chain is working. If the multiplexer named tx_src is switched over to its other input TX data is instead sourced from a streaming DMA. The stream DMA is reads a memory area out of RAM and transfers it as a stream of I/Q samples to the I/O interface. The CPU takes care of setting up the address and the length of the memory buffer, sends an activation signal and can then proceed to do other work until it gets an interrupt that all data has been sent.

On the receive side samples are streamed directly from the RF ASIC to the USB interface if no configuration is made. The samples are transmitted through USB in a format that is directly readable by the FFT Viewer in the LMS Suite. This allows users to view the received data on a computer without having to do any configuration of the FPGA registers. If instead rx_sink is switched to its other output the samples are sent to a RX stream DMA unit. The RX stream DMA reads samples from a stream and writes them to RAM through the Wishbone interface. The CPU sets up the address and size of the memory buffer to use, activates the DMA controller and can then do other things until the buffer is filled.

It has to be stated that a soft CPU running in an FPGA has nowhere near the capacity needed for any advanced signal processing, but what it can do is to make sure the OS runs and control the data flow through the signal processing chain.

All in all, STREAM is a fantastic little board that can be used as a general-purpose SDR platform straight away, and can be easily specialized for specific workloads by adding software or hardware accelerators in the data paths. And because both the board design files and the RTL code for the FPGA is open source, you can build, manufacture, sell and give away your own customized board based on the STREAM board design.

Olof Kindgren is working as a Digital Design Engineer at Qamcom Research & Technology in Göteborg, Sweden. Qamcom Research & Technology is a product development and specialist service provider in the areas of signal processing and communication systems, automotive systems and functional safety.