The Novena-RF daughtercard has a new driver to bring it into the ecosystem of SDR devices and applications.
The Novena-RF daughtercard incorporates an LMS6002D from Lime Microsystems, which gives users receive and transmit capabilities between 300 MHz and 3.8 GHz. The Novena motherboard contains a quad-core ARM processor from Freescale (iMX6) and a Spartan6 FPGA from Xilinx (XC6SLX45). The FPGA bridges the daughtercard to the extended memory bus of the iMX6, and provides DSP operations and advanced streaming control.
The Novena RF uses Soapy SDR to provide an easy to use API and access to a variety of existing applications. Soapy SDR provides C, C++, and Python interfaces to configure, control, and stream to and from a SDR device. In addition, gr-osmosdr and UHD applications are also available to the user through the Soapy SDR compatibility interfaces.
Direct buffer access
The Novena-RF driver was just the use-case that I needed to create a direct buffer access API for Soapy SDR. Direct buffer access avoids copying or converting stream buffers by providing the user with a pointer to the internal stream buffer. In the case of the Novena-RF driver, the user can directly access memory mapped stream buffers on the FPGA — which hopefully saves some extra arm cycles for the application. See the Soapy SDR doxygen for more about the new buffer API.
The novena_rf kernel module is responsible for configuring the iMX6’s extended memory bus (EIM), FPGA register access, and providing the driver with memory mapped stream buffers. After appropriate permissions are set for the device nodes, the driver can be used with normal non-root privilege mode.
Timed streaming and burst controls
The framer block is used for advanced control of the receive stream with controls for burst size and precise timestamping. The de-framer block is used for transmit, and it supports precisely timed transmit bursts and asynchronous error reporting. Both blocks support variable sample widths, and make use of the AXI4 stream standard to be used with other compliant AXI4 IP such as FIFOs and DSP blocks. In addition, an accompanying C header provides packet formatting and unpacking for the host driver.
Up/down conversion DSP chains
The LMS6002D transceiver provides an ADC/DAC rate of 15.36 Msps to the FPGA. The down conversion chain provides configurable decimation down to 480 ksps, in addition it has DC removal and a CORDIC for frequency correction and LO tuning offsets. The up conversion chain also sports a CORDIC, and provides configurable interpolation from 480 ksps up to DAC rate.
Streaming with DMA controllers
Everything ties into the iMX6 though the EIM bus. Hanging off the EIM bus, we have a register interface and several DMA controllers which interfaces between stream and memory domains. The register interfaces controls everything in the FPGA, including DSP chains, DMA controllers, time tracking and interrupts. The framer block uses a pair of DMA controllers for stream control (input) and stream data (output). The de-framer block uses another pair of controllers for stream data (input) and asynchronous notifications (output).
Anyone interested in getting involved with the Novena-RF driver should take a look at the Novena RF issue tracker on github. The FPGA DSP chains could be improved for additional corrections, configurable rates, scaling, and configurable sample formats for the direct buffer access feature. And its worth experimenting and investigating the EIM configuration parameters, and DMA buffer caching to improve stream throughput.
Top image: development setup (with added hamster for scale!)